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MC100EP140 3.3V ECL Phase-Frequency Detector
The MC100EP140 is a three state phase frequency-detector intended for phase-locked loop applications which require a minimum amount of phase and frequency difference at lock. Since the part is designed with fully differential internal gates, the noise is reduced throughout the circuit, especially at high speeds. The basic operation of a Phase/Frequency Detector (PFD) is to "compare" an incoming signal (feedback) to a set reference signal. When the Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase, the differential UP (U) and DOWN (D) outputs will provide pulse streams which, when subtracted and integrated, provide an error voltage for control of a VCO. Detector states of operation are shown in the Figure 2 and the State Table. The device is packaged in a small outline, surface mount 8-lead SOIC package. The typical output amplitude of the EP140 is 400 mV, allowing faster switching time and greater bandwidth. For proper operation, the input edge rate of the R and FB inputs should be less than 5 ns. More information on Phase Lock Loop operation and application can be found in AND8040. The pinout is shown in Figure 1, the logic diagram in Figure 3, and the typical termination in Figure 5.
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MARKING DIAGRAM
8 8 1 SO-8 D SUFFIX CASE 751 1 KP = MC100EP A = Assembly Location L = Wafer Lot Y = Year W = Work Week KP140 ALYW
* * * * *
500 ps Typical Propagation Delay Maximum Frequency > 2.1 GHz Typical Fully Differential Internally Advanced High Band Output Swing of 400 mV Transfer Gain: 1.0 mV/Degree at 1.4 GHz 1.2 mV/Degree at 1.0 GHz Rise and Fall Time: 100 ps Typical
ORDERING INFORMATION
Device MC100EP140D MC100EP140DR2 Package SO-8 SO-8 Shipping 98 Units/Rail 2500 Units/Reel
* * The 100 Series Contains Temperature Compensation * PECL Mode Operating Range: VCC = 3.0 V to 3.6 V * NECL Mode Operating Range: VCC = 0 V * Open Input Default State
with VEE = -3.0 V to -3.6 V with VEE = 0 V
(c) Semiconductor Components Industries, LLC, 2002
1
September, 2002 - Rev. 5
Publication Order Number: MC100EP140/D
MC100EP140
VCC 8 R 7 FB 6 VEE 5
PIN DESCRIPTION
PIN D, D U, U R* FB* VCC FUNCTION Differential Down Outputs Differential Up Outputs ECL Reference Input ECL Feedback Input Positive Supply Negative Supply
1 U
2 U
3 D
4 D
VEE
* Pins will default LOW when left open.
Figure 1. 8-Lead Pinout (Top View) STATE TABLE
R R PHASE DETECTOR STATE PUMP DOWN 2-1-2 2 2-1 1-2 2 FB FB PUMP UP 2-3-2 2 L H H L L L H L L H L L L L L L 2-3 3-2 2 INPUT R FB OUTPUT U D
FB
1
U= L D=H Pump Down
2
U=L D=L Pump Up
3
U=H D=L
R
L L H L
L H L L
L L L L
L H L L
Figure 2. Phase Detector Logic Model
U R A A S Reset VEE B D Reset FB D R B S D FF R U FF C D C A
C A
U U
Reset
Reset B D D D
B
Figure 3. Logic Diagram
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MC100EP140
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW 37.5 kW > 2 kV > 200 V > 2 kV Level 1 UL-94 V-0 @ 0.125 in 457 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout TA Tstg JA JC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode In ut Voltage Input NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 8 SOIC 8 SOIC 8 SOIC Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 -40 to +85 -65 to +150 190 130 41 to 44 265 Units V V V V mA mA C C C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Current Input LOW Current 0.5 Min 55 2155 1755 2075 1355 Typ 70 2280 1880 Max 85 2405 2005 2420 1675 150 0.5 Min 60 2155 1755 2075 1355 25C Typ 74 2280 1880 Max 90 2405 2005 2420 1675 150 0.5 Min 63 2155 1755 2075 1355 85C Typ 78 2280 1880 Max 93 2405 2005 2420 1675 150 Unit mA mV mV mV mV A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V. 4. All loading with 50 W to VCC-2.0 volts.
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MC100EP140
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.6 V to -3.0 V (Note 5)
-40C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Current Input LOW Current 0.5 Min 55 -1145 -1545 -1225 -1945 Typ 70 -1020 -1420 Max 85 -895 -1295 -880 -1625 150 0.5 Min 60 -1145 -1545 -1225 -1945 25C Typ 74 -1020 -1420 Max 90 -895 -1295 -880 -1625 150 0.5 Min 63 -1145 -1545 -1225 -1945 85C Typ 78 -1020 -1420 Max 93 -895 -1295 -880 -1625 150 Unit mA mV mV mV mV A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 5. Input and output parameters vary 1:1 with VCC. 6. All loading with 50 W to VCC-2.0 volts.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 7)
-40C Symbol fmax tPLH, tPHL tJITTER VPP tr tf Characteristic Maximum Frequency (See Figure 4 Fmax/JITTER) Propagation Delay to Output Differential Cycle-to-Cycle Jitter (See Figure 4 Fmax/JITTER) Input Voltage Swing Output Rise/Fall Times (20% - 80%) Q, Q 400 50 R to U, FB to D FB to U, R to D 300 400 Min Typ >2 450 600 .2 800 90 6002 800 <1 1200 180 400 60 325 450 Max Min 25C Typ >2 475 650 .2 800 100 625 850 <1 1200 200 400 70 350 500 Max Min 85C Typ >2 500 700 .2 800 120 650 900 <1 1200 220 Max Unit GHz ps ps mV ps
7. Measured using a 750 mV VPP pk-pk, 50% duty cycle, clock source. All loading with 50 W to VCC-2.0 V.
600
6
500 VOUTpp (mV)
400
4 3 2
300
200
100
IIIIIIIIIIIIIIII II IIIIIIIIIIIIIIII II IIIIIIIIIIIIIIII II
(JITTER) 1 0 0 400 800 1200 1600 2000 2400 FREQUENCY (MHz)
Figure 4. Fmax/Jitter
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JITTEROUT ps (RMS)
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MC100EP140
Q Driver Device Q 50 W 50 W
D Receiver Device D
V TT V TT = V CC - 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1504 AN1568 AN1650 AN1672 AND8001 AND8002 AND8009 AND8020 AND8040
- - - - - - - - - - - -
ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices Phase Lock Loop Operation
For an updated list of Application Notes, please see our website at http://onsemi.com.
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MC100EP140
PACKAGE DIMENSIONS
SO-8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-07 ISSUE AA
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDAARD IS 751-07 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
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MC100EP140
Notes
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MC100EP140
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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MC100EP140/D

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